Computer Architecture Ii
A.Y. 2024/2025
Learning objectives
The course provides the knowledge of the digital architectures and in particular of pipelines, multi-core and memory hierarchies better understand operating systems and to deeply understand how software can be optimized. The instruments for a quantitative evaluation of an architecture are also provided.
Expected learning outcomes
The student will be able to understand how pipeline and multicore architectures work, how memory hierarchies are handled and what is the hardware support to virtual memory;
(s)he will understand the types of connections between different components and the various policies to handle I/O. The student will have the tools needed to evaluate computer performances and to optimize applications.
(s)he will understand the types of connections between different components and the various policies to handle I/O. The student will have the tools needed to evaluate computer performances and to optimize applications.
Lesson period: Second semester
Assessment methods: Esame
Assessment result: voto verbalizzato in trentesimi
Single course
This course cannot be attended as a single course. Please check our list of single courses to find the ones available for enrolment.
Course syllabus and organization
Edition 1
Responsible
Lesson period
Second semester
Course syllabus
THEORY
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core.
Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory
Input/Output and evaluation metric.
LABORATORY
Laboratory on writing correctly programs in assembly language.
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core.
Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory
Input/Output and evaluation metric.
LABORATORY
Laboratory on writing correctly programs in assembly language.
Prerequisites for admission
None. It is suggested to follow this course after Architettura degli Elaboratori I.
Teaching methods
Frontal lessons + laboratory
Frequency modality: in presence.
Frequency modality: in presence.
Teaching Resources
Basic text (available in both English and Italian):
· "Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, New Sixth Edition, 2020. NB Morgan Kaufman also published a version of the text for RISC-V and for ARM, not adopted in this course.
·
· "Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, New Sixth Edition, 2020. NB Morgan Kaufman also published a version of the text for RISC-V and for ARM, not adopted in this course.
·
Assessment methods and Criteria
The evaluation is performed through a written exam followed by an oral exam and a laboratory test.
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
The laboratory test consists of a realization on a PC of a set of exercises of digital architecture design.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
The laboratory test consists of a realization on a PC of a set of exercises of digital architecture design.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Professors:
Borghese Nunzio Alberto, Tarini Marco
Shifts:
Turno
Professor:
Borghese Nunzio AlbertoTurno A
Professor:
Tarini MarcoEdition 2
Responsible
Lesson period
Second semester
Course syllabus
For the theory part:
- Single-cycle and multiple-cycle CPU: pipeline, criticalities, interrupts, exceptions, and their management;
- static and dynamic memory, virtual memory, memory hierarchy;
- input/output;
- performance evaluation metrics.
For the laboratory part, in addition to a tutorial on the use of software tools, sessions will propose Assembly programming exercises covering the following topics:
- use of memory;
- system calls;
- flow control;
- definition and call to procedures;
- handling of exceptions.
The theory and laboratory parts are carried out in parallel. The beginning of the lab sessions is usually delayed of one/two weeks.
- Single-cycle and multiple-cycle CPU: pipeline, criticalities, interrupts, exceptions, and their management;
- static and dynamic memory, virtual memory, memory hierarchy;
- input/output;
- performance evaluation metrics.
For the laboratory part, in addition to a tutorial on the use of software tools, sessions will propose Assembly programming exercises covering the following topics:
- use of memory;
- system calls;
- flow control;
- definition and call to procedures;
- handling of exceptions.
The theory and laboratory parts are carried out in parallel. The beginning of the lab sessions is usually delayed of one/two weeks.
Prerequisites for admission
Attendance of the course Computer Architecture I is suggested.
Teaching methods
The theory part is given with frontal lectures where slides are presented. Slides are made available in PDF format through the myAriel platform.
The laboratory part proposes guided exercising sessions at the PC. The adopted software tools and the exercises (instructions and selected solutions) are made available through the Ariel platform.
Attendance is recommended for both the theory and the laboratory part.
The laboratory part proposes guided exercising sessions at the PC. The adopted software tools and the exercises (instructions and selected solutions) are made available through the Ariel platform.
Attendance is recommended for both the theory and the laboratory part.
Teaching Resources
Both the theory and the laboratory part are based on the topics covered in: "Computer Organization & Design: The Hardware/Software Interface" by David A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers.
For further support, slides, exercises, and other supplementary material are provided during the course on the myAriel platform.
For further support, slides, exercises, and other supplementary material are provided during the course on the myAriel platform.
Assessment methods and Criteria
For the theory part, there will be a written test lasting at most 3 hours where the resolution of an adequate number of exercises is proposed. Each exercise involves the application of the principles and techniques presented during the lectures. During the exam, consulting any material is forbidden. "In itinere" tests could be done during the course.
For the laboratory part, the exam consists in carrying out some proposed exercises on the PC and lasts about 1 hour. Each exercise requires writing an Assembly program for the MIPS architecture according to specific functional requirements. During the exam, specific material approved by the teacher can be consulted.
Both tests, theory and laboratory, result in a grade out of thirty which is communicated through the Ariel platform (optionally also by email). If both grades are greater than or equal to 18, the exam is passed with a grade equal to the weighted average of the theory grade (weight 2/3) and the laboratory grade (weight 1/3). The two tests can be passed in different exam sessions but in a time span of at most three successive exam sessions or six months (the less restrictive rule will be applied).
The assessments will take into account: confidence in applying techniques, correctness and elegance of the solutions, clarity of presentation. The tests and their assessments will not be differentiated on the basis of attendance.
For the laboratory part, the exam consists in carrying out some proposed exercises on the PC and lasts about 1 hour. Each exercise requires writing an Assembly program for the MIPS architecture according to specific functional requirements. During the exam, specific material approved by the teacher can be consulted.
Both tests, theory and laboratory, result in a grade out of thirty which is communicated through the Ariel platform (optionally also by email). If both grades are greater than or equal to 18, the exam is passed with a grade equal to the weighted average of the theory grade (weight 2/3) and the laboratory grade (weight 1/3). The two tests can be passed in different exam sessions but in a time span of at most three successive exam sessions or six months (the less restrictive rule will be applied).
The assessments will take into account: confidence in applying techniques, correctness and elegance of the solutions, clarity of presentation. The tests and their assessments will not be differentiated on the basis of attendance.
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Shifts:
Turno
Professor:
Basilico NicolaTurno B
Professor:
Re' MatteoTurno C
Professor:
Luperto MatteoProfessor(s)
Reception:
Tuesday 14:30-17:30 (or by appointment)
Department (Via Celoria 18) -- Office 4006.