Computer Architecture Ii

A.Y. 2018/2019
6
Max ECTS
60
Overall hours
SSD
INF/01
Language
Italian
Learning objectives
Fornire la conoscenza dei componenti principali dei calcolatori
Fornire la conoscenza dei principi di funzionamento dei diversi componenti e delle loro connessioni.
Fornire gli strumenti per valutare le prestazioni dei calcolatori e per ottimizzare le applicazioni.
Expected learning outcomes
Undefined
Single course

This course cannot be attended as a single course. Please check our list of single courses to find the ones available for enrolment.

Course syllabus and organization

Milan

Lesson period
Second semester
ATTENDING STUDENTS
Course syllabus
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core.
Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory
Input/Output and evaluation metric.
Laboratory on writing correctly programs in assembly language.
NON-ATTENDING STUDENTS
Course syllabus
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core.
Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory
Input/Output and evaluation metric.
Laboratory on writing correctly programs in assembly language.
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Shifts:
Turno A
Professor: Basilico Nicola
Turno B
Professor: Tarini Marco
Professor(s)
Reception:
Tuesday 14:30-17:30 (or by appointment)
Department (Via Celoria 18) -- 4th floor.