Computer Architecture I
A.Y. 2019/2020
Learning objectives
The course introduces the principles at the base of a computer; simple logic gates are first presented, and then combined, thought a succession of intermediate abstraction layers, into the design of ALU firmware and of a MIPS architecture, capable of executing programs with a core machine language.
Expected learning outcomes
The student will be familiar with the basic principles underlying the processing of digital information. In particular, (s)he will have the skills needed to understand, analyze and design
combinatorial and sequential circuits.
combinatorial and sequential circuits.
Lesson period: First semester
Assessment methods: Esame
Assessment result: voto verbalizzato in trentesimi
Single course
This course cannot be attended as a single course. Please check our list of single courses to find the ones available for enrolment.
Course syllabus and organization
Edition 1
Responsible
Lesson period
First semester
Course syllabus
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
Design and realization of logical circuits through a simulator.
[Program for not attending students with reference to descriptor 1 and 2]:
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
Design and realization of logical circuits through a simulator.
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
Design and realization of logical circuits through a simulator.
[Program for not attending students with reference to descriptor 1 and 2]:
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
Design and realization of logical circuits through a simulator.
Prerequisites for admission
None
Teaching methods
a) Frontal lessons + b) Laboratory on the subject
Teaching Resources
Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, Fifth Edition, 2014. Potete trovare materiale integrativo al seguente URL: http://books.elsevier.com/companions/1558606041/. Notice that Morgan Kaufman has published also a version of the book based on RISC-V and one based on ARM. They have not been adopted for this course.
Assessment methods and Criteria
The evaluation is performed through a written exam followed by an oral exam and a laboratory test.
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
The laboratory test consists of a realization on a PC of a set of exercises of digital architecture design.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
The laboratory test consists of a realization on a PC of a set of exercises of digital architecture design.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Shifts:
-
Professor:
Borghese Nunzio AlbertoTurno A
Professor:
Basilico NicolaTurno B
Professor:
Trucco GabriellaEdition 2
Responsible
Lesson period
First semester
Course syllabus
For the theory part:
Lesson 00 - Intro to the course
Lesson 01 - Machines and Languages
Lesson 02 A Representations: of natural
Lesson 02 B Representations: of integers
Lesson 02 C Representations: in scientific notation
Lesson 02 D Representations: floating point
Lesson 02 E Representations: of texts
Lesson 02 F Representations: of texts - beyond ASCII
Lesson 03 A Logic gates and circuits: operation
Lesson 03 B Logic gates and circuits: examples
Lesson 04 - Synthesis of combinatorial circuits
Lesson 05 A Functional combinatorial blocks: DEC, COD, MUX
Lesson 05 B Functional combinatorial blocks: ADD, SFT, MUL
Lesson 06 - The ALU
Lesson 07 - PLA, ROM, EEPROM, FPGA
Lesson 08 - Bistables, Flip-Flip and synchronization
Lesson 09 A Finite State Machine: graph
Lesson 09 B Finite State Machine: tables and circuits
Lesson 10 - Registers
Lesson 11 A Register File: intro, single bus
Lesson 11 B Register File: read command
Lesson 12 - Memory (outline)
Lesson 13 - Bus (outline)
Lesson 14 A Single Cycle CPU: MIPS Intro and Op registers
Lesson 14 B Single Cycle CPU: Op. With immediate, RAM op.
Lesson 14 C CPU Single Cycle: Jumps and Branches
Lesson 14 E Single Cycle CPU: Analysis
Lesson 14 D Single Cycle CPU: the Control unit
Lesson 15 - Multicycle CPU
Lesson 16 A Firmware (for ALU) - Multiplication
Lesson 16 B Firmware (for ALU) - Microprogram and Division.
Lesson 00 - Intro to the course
Lesson 01 - Machines and Languages
Lesson 02 A Representations: of natural
Lesson 02 B Representations: of integers
Lesson 02 C Representations: in scientific notation
Lesson 02 D Representations: floating point
Lesson 02 E Representations: of texts
Lesson 02 F Representations: of texts - beyond ASCII
Lesson 03 A Logic gates and circuits: operation
Lesson 03 B Logic gates and circuits: examples
Lesson 04 - Synthesis of combinatorial circuits
Lesson 05 A Functional combinatorial blocks: DEC, COD, MUX
Lesson 05 B Functional combinatorial blocks: ADD, SFT, MUL
Lesson 06 - The ALU
Lesson 07 - PLA, ROM, EEPROM, FPGA
Lesson 08 - Bistables, Flip-Flip and synchronization
Lesson 09 A Finite State Machine: graph
Lesson 09 B Finite State Machine: tables and circuits
Lesson 10 - Registers
Lesson 11 A Register File: intro, single bus
Lesson 11 B Register File: read command
Lesson 12 - Memory (outline)
Lesson 13 - Bus (outline)
Lesson 14 A Single Cycle CPU: MIPS Intro and Op registers
Lesson 14 B Single Cycle CPU: Op. With immediate, RAM op.
Lesson 14 C CPU Single Cycle: Jumps and Branches
Lesson 14 E Single Cycle CPU: Analysis
Lesson 14 D Single Cycle CPU: the Control unit
Lesson 15 - Multicycle CPU
Lesson 16 A Firmware (for ALU) - Multiplication
Lesson 16 B Firmware (for ALU) - Microprogram and Division.
Prerequisites for admission
No prerequisites are needed. All topics are covered without any assumption than the normal preparation provided by any high school. In particular, no previous computer knowledge is required.
Teaching methods
For the theory part: lessons.
Teaching Resources
The web-page of the course provides lecture slides and additional material: https://mreae1.ariel.ctu.unimi.it/ for both the theory and the lab parts.
The course closely follows the following textbook
"Architettura degli elaboratori" J. L. Hennessy, D. A. Patterson (qualsiasi edizione)
The course closely follows the following textbook
"Architettura degli elaboratori" J. L. Hennessy, D. A. Patterson (qualsiasi edizione)
Assessment methods and Criteria
The exam is divided into two parts: theory and laboratory. The final mark is the weighted average between the two marks obtained in the two parts, with weights 2/3 and 1/3 respectively.
FOR THE PART OF THEORY:
Written test lasting 2 hours, which consists of the solution of exercises related to the topics covered in the teaching, and the answer to short open questions.
The written test can be entirely replaced by two on-going tests, each of which covers one half of the course, which are held during the semester of delivery. Both ongoing tests must be passed in order to replace the writing.
The evaluation of the theoretical part is aimed at verifying the full understanding of the topics covered in the course, the acquisition of the technical vocabulary proper to the discipline, and, primarily, the ability to apply the analysis and synthesis methods imparted in the teaching.
FOR THE PART OF THEORY:
Written test lasting 2 hours, which consists of the solution of exercises related to the topics covered in the teaching, and the answer to short open questions.
The written test can be entirely replaced by two on-going tests, each of which covers one half of the course, which are held during the semester of delivery. Both ongoing tests must be passed in order to replace the writing.
The evaluation of the theoretical part is aimed at verifying the full understanding of the topics covered in the course, the acquisition of the technical vocabulary proper to the discipline, and, primarily, the ability to apply the analysis and synthesis methods imparted in the teaching.
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Professors:
Re' Matteo, Tarini Marco
Shifts:
-
Professor:
Tarini MarcoTurno C
Professor:
Re' MatteoProfessor(s)
Reception:
Tuesday 14:30-17:30 (or by appointment)
Department (Via Celoria 18) -- 4th floor.