The course provides the knowledge of the digital architectures and in particular of pipelines, multi-core and memory hierarchies better understand operating systems and to deeply understand how software can be optimized. The instruments for a quantitative evaluation of an architecture are also provided.
Expected learning outcomes
The student will be able to understand how pipeline and multicore architectures work, how memory hierarchies are handled and what is the hardware support to virtual memory; (s)he will understand the types of connections between different components and the various policies to handle I/O. The student will have the tools needed to evaluate computer performances and to optimize applications.
Lesson period: Second semester
(In case of multiple editions, please check the period, as it may vary)
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core. Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory Input/Output and evaluation metric. Laboratory on writing correctly programs in assembly language.
Prerequisites for admission
None. It is suggested to follow this course after Architettura degli Elaboratori II.
frontal lessons + laboratory
Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, New Fifth Edition, 2014. Potete trovare materiale integrativo al seguente URL: http://books.elsevier.com/companions/1558606041/.
Assessment methods and Criteria
The evaluation is performed through a written exam followed by an oral exam and a laboratory test. In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program. The laboratory test consists of a realization on a PC of a set of exercises of digital architecture design. Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams. In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.