Computer Architecture Ii
A.Y. 2026/2027
Learning objectives
The course provides the knowledge of the digital architectures and in particular of pipelines, multi-core and memory hierarchies better understand operating systems and to deeply understand how software can be optimized. The instruments for a quantitative evaluation of an architecture are also provided.
Expected learning outcomes
The student will be able to understand how pipeline and multicore architectures work, how memory hierarchies are handled and what is the hardware support to virtual memory;
(s)he will understand the types of connections between different components and the various policies to handle I/O. The student will have the tools needed to evaluate computer performances and to optimize applications.
(s)he will understand the types of connections between different components and the various policies to handle I/O. The student will have the tools needed to evaluate computer performances and to optimize applications.
Lesson period: Second semester
Assessment methods: Esame
Assessment result: voto verbalizzato in trentesimi
Single course
This course cannot be attended as a single course. Please check our list of single courses to find the ones available for enrolment.
Course syllabus and organization
Group 1
Responsible
Lesson period
Second semester
Course syllabus
THEORY
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core.
Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory
Input/Output and evaluation metric.
LABORATORY
Laboratory on writing correctly programs in assembly language.
Introduction. CPU and UC single cycle, multi-cycle and pipelined. Hazard and stalls. Advanced pipelines: multiple-issue and multi-core.
Interrupts and exceptions. HW processing of exceptions. Memory hierarchy. Virtual memory
Input/Output and evaluation metric.
LABORATORY
Laboratory on writing correctly programs in assembly language.
Prerequisites for admission
None. It is suggested to follow this course after Architettura degli Elaboratori I.
Teaching methods
a) Frontal lessons + b) Laboratory on the subject. Attending lessons and laboratory is strong advised.
Teaching Resources
Basic text (available in both English and Italian):
· "Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, New Sixth Edition, 2020. NB Morgan Kaufman also published a version of the text for RISC-V and for ARM, not adopted in this course.
·
· "Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, New Sixth Edition, 2020. NB Morgan Kaufman also published a version of the text for RISC-V and for ARM, not adopted in this course.
·
Assessment methods and Criteria
The evaluation is performed through a written exam followed by an oral exam and a laboratory test.
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
For the laboratory part, the exam, lasts about 3 hours and it consists in the realization of a small complete project: combinatorial + sequential circuit. During the exam the student can browse through the material provided by the teacher.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all the three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
The written exam and the laboratory exam can be sustained in different rounds, but inside a time span no longer than 6 months or three consecutive rounds (the least restrictive applies).
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
For the laboratory part, the exam, lasts about 3 hours and it consists in the realization of a small complete project: combinatorial + sequential circuit. During the exam the student can browse through the material provided by the teacher.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all the three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
The written exam and the laboratory exam can be sustained in different rounds, but inside a time span no longer than 6 months or three consecutive rounds (the least restrictive applies).
INFO-01/A - Informatics - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Professors:
Borghese Nunzio Alberto, Tarini Marco
Group 2
Responsible
INFO-01/A - Informatics - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Professor:
Re' Matteo
Professor(s)
Reception:
Tuesday 14:30-17:30 (or by appointment)
Department (Via Celoria 18) -- 4th floor.